The support for interposer trace lengths gives designers more flexibility in the PHY placement without impacting performance. The DesignWare HBM3 PHY utilizes an optimized micro bump array to help minimize area. The DesignWare HBM3 PHY IP in 5-nm process, available as pre-hardened or customer configurable PHY, operates at up to 7200 Mbps per pin, significantly improves power efficiency and supports up to four active operating states enabling dynamic frequency scaling. The controller minimizes latency and optimizes data integrity with advanced RAS features that include error correction code, refresh management and parity.
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Synopsys' DesignWare HBM3 Controller IP supports a variety of HBM3-based systems with flexible configuration options. To accelerate development of HBM3 system designs, Synopsys' 3DIC Compiler multi-die design platform provides a fully integrated architectural exploration, implementation and system-level analysis solution.
SYNOPSYS MOUNTAIN VIEW VERIFICATION
The Synopsys verification solution, including Verification IP with built-in coverage and verification plans, off-the-shelf HBM3 memory models for ZeBu® emulation, and HAPS® prototyping system, accelerates verification from HBM3 IP to SoCs. Synopsys' DesignWare® HBM3 Controller and PHY IP, built on silicon-proven HBM2E IP, leverage Synopsys' interposer expertise to provide a low-risk solution that enables high memory bandwidth at up to 921 GB/s. HBM3 technology helps designers meet essential high-bandwidth and low-power memory requirements for system-on-chip (SoC) designs targeting high-performance computing, AI and graphics applications. Synopsys, Inc. (Nasdaq: SNPS) today announced the industry's first complete HBM3 IP solution, including controller, PHY, and verification IP for 2.5D multi-die package systems.
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Low-latency HBM3 Controller with flexible configuration options enhance memory bandwidth.The DesignWare HBM3 Controller, PHY, and Verification IP reduces integration risk and maximizes memory performance in 2.5D multi-die systems.